A New Memory Controller by Manchester Encoder & Linear Feedback Shift Register by Pseudo Random Sequence Generator

Mr. S.Mohan Das, Mr. M. Mahaboob Basha, Mrs. Sompalli Madhuri


In this paper a plenarily reused VLSI architecture of FM0/Manchester encoding technique for recollection application has been proposed. In this paper we are encoding the 1 bit data into 16 bit data and storing it into a recollection of certain address location given by the linear feedback shift register (LFSR),whose input is taken from the pseudo arbitrary sequence engenderer (PRSG). The encoded 16 bit data is stored into recollection controller; the encoded data is decoded back into 1 bit data under the condition: when MSB bit is at logic state 1. By utilizing FM0/Manchester encoding and decoding technique, the data will be secure; this process is facile and more expeditious to carry out. This paper develops a plenarily reused VLSI architecture, and additionally exhibits an efficient performance.

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Copyright (c) 2016 Mr. S.Mohan Das, Mr. M. Mahaboob Basha, Mrs. Sompalli Madhuri

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