A Novel Access speed Data Retention Time Reliable Gain cell Low power operation

Abstract

Memories have occupied increasingly large portions of the die area of VLSI systems-on-chip (SoCs), in general, and of microprocessor. This is due to the large 6-transistor (6T) SRAM bitcell and its area-consuming peripheral circuitry that are the basis for the vast majority of these. In addition, the standby power of ultralow-power (ULP) systems, such as biomedical implants and wireless sensor networks, is often dominated by embedded memories, which continue to leak during the long retentive standby periods that characterize these systems. Logic compatible gain cell (GC)-embedded DRAM (eDRAM) arrays are considered an alternative to SRAM due to their small size, nonratioed operation, low static leakage, and two-port functionality. However, traditional GC-eDRAM implementations require boosted control signals in order to write full voltage levels to the cell to reduce the refresh rate and shorten access times. These boosted levels require an extra power supply or on-chip charge pumps, as well as nontrivial level shifting and toleration of high voltage levels. In this brief, we present a novel, logic compatible, 3T GC-eDRAM bitcell that operates with a single-supply voltage and provides superior write capability to the conventional GC structures.