Survey on Compressor & Dadda Multiplier Inexact Computing Approximate Circuits

Abstract

Multipliers are usually deemed as a critical component in digital signal processor design since a large number of multiplications are required in DSP applications. Inexact (or approximate) computing is an attractive paradigm for digital processing at nano metric scales. Inexact computing is particularly interesting for computer arithmetic designs. This paper deals with the analysis and design of two new approximate 4-2 compressors for utilization in a multiplier. These designs rely on different features of compression, such that imprecision in computation can meet with respect to circuit-based figures of merit of a design. Four different schemes for utilizing the proposed approximate compressors are proposed and analyzed for a Dadda multiplier. Binary logarithms can be used to perform computer multiplication through simple addition. Exact logarithmic conversion is prohibitively expensive for use in general multipliers; however, inexpensive estimate conversions can be used to perform approximate multiplication. Such approximate multipliers have been used in domain-specific applications, but existing designs either offer superior efficiency or flexibility. The results show that the prop osed designs accomplish significant reductions in power dissipation, delay and transistor count compared to an exact design.