DESIGN AN AGING-AWARE RELIABLE H- MULTIPLIER

Abstract

This paper presents the design anH-Logic[H.L] multiplierfor 32*32bit number multiplication. Modern computer system is a dedicated with very high speed unique multiplier. Therefore, this paper presents the design anH-Logic multiplier. The proposed system generates M,N and X blocks. By extending bit of the operands and generating an additional product the H-Logic multiplier is obtained. Multiplication operation is performed by the H-Logicis efficient with the less area anditgives the reduces delay i.e., speed is increased.