An Area Efficient Multiplier Design Using Fixed-Width Replica Redundancy

Abstract

In this paper, proposedAn Area Efficient Multiplier Design Using Fixed-Width Replica Redundancy by adopting algorithmic noise tolerant (ANT) architecture with the fixed-width multiplier to build the reduced precision replica redundancy block (RPR). The proposed ANT architecture can meet the demand of high precision, low power consumption, and area efficiency. We design the fixed-width RPR with error compensation circuit via analysing of probability and statistics. Using the partial product terms of input correction vector and minor input correction vector to lower the truncation errors, the hardware complexity of error compensation circuit can be simplified. In a 16 × 16 bit ANT multiplier, circuit area in our fixed-width RPR can be lower and power consumption in our ANT design can be saved as compared with the state-of-art ANT design.