An Optimized Design Of High-Speed And Energy Efficient Carry Skip Adder with Variable Latency Extension

Abstract

The portable equipments such as cellular phones, Personal Digital Assistant (PDA), and notebook personal computer, arise the need of effective circuit area and power efficient VLSI circuits. Addition is the most common and often used arithmetic operation in digital computers and also, it serves as a building block for synthesis all other arithmetic operations. Low-power and high-speed adder cells (like carry skip adder) are used in battery operation based devices. Now the biggest challenge is reduction of adder power consumption and delay while maintaining the high performance in different types of circuit design. In conventional carry skip adder the multiplexer is used as a skip logic that provides a better performance and performs an efficient operation with the minimum circuitry. Even though, it affords a significant advantages there may be a large critical path delay revealed by the multiplexer and also it containing twelve transistors that leads to increase of area usage and power consumption. The proposed method uses compound gates such as AOI and OAI as skip logic in the design that leads to decrease area usage, delay and power consumption, also in addition the parallel prefix adder is included to attain further reduction of power. The design is coded in VHDL and simulated in ModelSim and its area, delay and power are analyzed using Xilinx_ISE 9.2i.