DESIGN AN AGING-AWARE RELIABLE MULTIPLIER WITH D- LOGIC

Abstract

This paper presents the design an D-Logic [D.L.L] multiplier for 32*32 bit number multiplication. Modern computer system is a dedicated and very high speed unique multiplier. Therefore, this paper presents the design an D-Logic multiplier. The proposed system generates M,N and interconnected blocks. By extending bit of the operands and generating an additional product the D-Logic multiplier is obtained. Multiplication operation is performed by the D-Logic is efficient with the less area and it reduces delay i.e., speed is increased.