Design of Digit-Serial Fir Filters Using Mag Adder Graph Multiplier

Abstract

Finite Impulse Response (FIR) filters are widely applied in multistandard wireless communications. A novel efficient algorithms and architectures have been introduced for the design of low complexity bit-parallel multiple constant multiplications (MCM) operation which dominates the complexity of many digital signal processing systems. In digit-serial MCM design that offers low complexity MCM operations that offers a low delay. In this previous design a MCM operations performed by CSE algorithm but it occupies large and delay area. In MCM design based Graph algorithm provides low area and delay. In this we proposed a MAG multiplier based on graph architecture for implementing low complexity higher order FIR filters.