Low Power Testable Reversible Sequential Circuits implementation on FPGA

Abstract

In this paper suggested reversible sequential circuits based on conservative logic that's checkable for any unidirectional  stuck-at faults using only 2 test vectors, that consists of all 0s and all 1s. So our novel proposed sequential circuits basically depends on particular conservative logic gates that role is to exceed the sequential circuit as previously realized in classical gates in the case of testability. As mentioned the considered sequential circuit’s implemented by employing typical classic gates don't offer heritable support for testability. Hence, a standard sequential circuit desires modification within the unique circuitry, its role is to offer the testing capability. We have a tendency to for presenting a brand new conservative gate referred to as multiplexer conservative QCA gate (MX-cqca) that's not reversible in nature nevertheless has analogous properties because the Fredkin gate seem to be operating as 2:1 multiplexer.  At last our proposed MX-cqca gate surpasses the Fredkin gate as far as many-sided quality (the quantity of larger majority voters), speed, and area.