Implementation and Design of High Performance 128 bit parallel prefix MAC unit

Abstract

Digital signal processing (DSP) applications, the critical operations usually involve many multiplications and/or accumulations. So, for real time signal processing applications, high throughput multiplier–accumulator (MAC) is always a key element to achieve a high-performance digital signal processing application. This is because speed and throughput rate are always the concerns of digital signal processing systems. This is because the limited battery energy of these portable products restricts the power consumption of the system. The multiplier is designed using single precision multiplier and the adder is done with parallel prefix adder. The total operation is coded with VERILOG-HDL, synthesized and simulated using Xillinx ISE 14.7.