A Noval SP Kernel Finder & Kernel Composition using Tanner Tool

Abstract

This paper presents an incipient methodology to engender efficient transistor networks. Transistor-level optimization consists in an efficacious possibility to increment design quality when engendering CMOS logic gates to be inserted in standard cell libraries. Starting from an input ISOP, the proposed method is able to distribute series-parallel and non-series-parallel arrangements with reduced transistor count. The experiments performed over the set of 4-input P-class Booleans functions have demonstrated the efficiency of the proposed approach.