VDigital signal processing Using filter truncated multipliers By VLSI design

Abstract

Low-cost finite impulse replication (FIR) designs are presented utilizing the concept of multipliers with the optimization of bit width and hardware resources without sacrificing the frequency replication and output signal precision. Non-uniform coefficient quantization with opportune filter order is proposed to minimize total area and cost. Multiple constant multiplication/accumulation in a direct FIR structure is implemented utilizing an amended version of Booth multipliers. In this proposed method a booth multiplier is implemented. In Booth multiplier to multiply the signed numbers is an integrated advantage. Comparisons with antecedent FIR design approaches show that the proposed designs achieve the best area and power results.