A Novel Architecture For High Performancet.L - Multiplier

Shaik. Shehanaz, T. Revathi


This paper presents the design an trigic logic [T.L] multiplier for 32*32 bit number multiplication. Modern computer system is a dedicated and very high speed unique multiplier. Therefore, this paper presents the design an trigic logic multiplier. The proposed system generates M,N and interconnected blocks. By extending bit of the operands and generating an additional product the trigic logic multiplier is obtained. Multiplication operation is performed by the trigic logic is efficient with the less area and it reduces delay i.e., speed is increased.


T.L, partial products, trigic logic unit.

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