An Enhanced and Optimized FIFO Based Testing Using VLSI

Abstract

The on line transparent test technique for detection of latent hard faults which develop in first input first output  buffers of routers during field operation of NOC and also propose fault tolerant solution by introducing shared  buffer in router. It provides alternative way in case of detection of faults otherwise used to improve efficiency.  The technique involves repeating tests periodically to prevent accumulation of faults. NOC approach has emerged as a promising solution for on   chip communications. This proposes an on   line transparent test  technique for detection of latent hard faults which develop in first input first output buffers of routers during  field operation of NOC. The technique involves repeating tests periodically to prevent accumulation of faults.  Further this project can be enhanced by using scan chain reordering technique. Time optimization is main criteria in this enhancement.