A Novel Architecture For High Performance T.L - Multiplier

Abstract

This paper presents the design an trigic logic [T.L] multiplier for 32*32 bit number multiplication. Modern system of computer is a unique multiplier which is a very high speed and dedicated. Therefore, this paper presents the design an tragic logic multiplier. The proposed system generates M,N and interconnected blocks. By extending bit of the operands and generating an additional product the trigic logic multiplier is obtained. Multiplication operation is performed by the trigic logic is efficient with the less area and it reduces delay i.e., speed is increased.