Reliable multiplier for positive bias temperature instability suing AHL & NBTI

Abstract

Digital multipliers are among the most critical arithmetic functional units. The overall performance of the Digital multiplier systems depends on throughput of the multiplier. The negative partialness temperature instability effect occurs when a pMOS transistor is under negative inequitableness (Vgs = −Vdd), incrementing the threshold voltage of a pMOS transistor and reducing the multiplier celerity. Similarly, positive inequitableness temperature instability occurs when an nMOS transistor is under positive partialness. Both effects degrade the celerity of the transistor and in the long term, the system may be fail due to timing contravention. Ergo, it is required to design reliable high-performance multipliers. In this paper, we implement an agingaware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide the higher throughput through the variable latency and can adjust the adaptive hold logic (AHL) circuit to abate performance degradation that is due to the aging effect. The proposed design can be applied to the column bypass multiplier.