Design and Implementation of High Throughput Multiplier

Abstract

Design of a high performance and high density multiplier is presented. This multiplier is constructed by using the Delay efficient carry skip adder. In previous we read about the designing of multipliers using the ripple carry adders and carry select adders. By using the ripple carry adders and carry select adders the propagation delay is high. In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrimination schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and energy parameters of the adder.The proposed multiplier design involves significantly less delay than the recently proposed multipliers using carry select adders. The results are synthesized using Xilinx 13.2 Software and simulated using Modelsim Software.