Area–Delay–Power Efficient Carry-Select Adder

Abstract

In this brief, the logic operations involved in conventional carry select adder (CSLA) and binary to excess-1 converter (BEC)-based CSLA are analyzed to study the data dependence and to identify redundant logic operations. We have eliminated all the redundant logic operations present in the conventionalCSLA and proposed a new logic formulation for CSLA. In the proposed scheme, the carry select (CS) operation is scheduledbefore the calculation of final-sum, which is different from the conventionalapproach. Bit patterns of two anticipating carry words (corresponding to cin = 0 and 1) and fixed cin bits are used for logic optimization of CS and generation units. An efficient CSLAdesign is obtained using optimized logic units. The proposed CSLAdesign involves significantly less area and delay

than the recentlyproposed BEC-based CSLA. Due to the small carry-

Outputdelay, the proposed CSLA design is a good candidate for square-root(SQRT) CSLA. A theoretical estimate shows that the proposedSQRT-CSLA involves nearly 35% less area–delay–product (ADP)than the BEC-based SQRT-CSLA, which is best among the existingSQRT-CSLA designs, on average, for different bit-widths.The application-specified integrated circuit (ASIC) synthesis resultshows that the BEC-based SQRT-CSLA design involves 48%more ADP and consumes 50% more energy than the proposedSQRT-CSLA, on average, for different bit-widths.