Implementation of Low Power Full Adder Using Semi XOR Semi XNOR on 120 nm Technology

Abstract

In present work a new XNOR gate using three transistors has been presented, which shows powerdissipation of 550.7272μW in 0.12μm technology with supply voltage of 1.5V. Minimum level for highoutput of 2.05V and maximum level for low output of 0.084V have been obtained. A single bit full adderusing eight transistors has been designed using proposed XNOR cell, which shows power dissipation of581.542μW. Minimum level for high output of 1.97V and maximum level for low output of 0.24V isobtained for sum output signal. For carry signal maximum level for low output of 0.32V and minimum levelfor high output of 3.2V have been achieved. Simulations have been performed by using TPICE based on0.12μm CMOS technology. Power consumption of proposed XNOR gate and full adder has beencompared with earlier reported circuits and proposed circuit’s shows better performance in terms of powerconsumption and transistor count.