Power optimization of dual modulus prescaler for higher frequency using GDI technique

Abstract

The coexistence of different cellular system demands reconfigurable mobile terminals. For greater degree of application such as Text, graphics, audio and games etc are required to handle by modern handset. These demands can be fulfilled by integrating some Complementary technologies such as WLAN or Bluetooth, UWB for high bandwidth local or personal services and 2G — 3G standards for voice low data rate communication with wide area coverage together in same handset. Frequency dividers are useful in many communication applications such as Frequency synthesizers, Timing recovery circuits and clock generations. The design of frequency divider is an important factor in performance of PLL as it is in feedback path and so locking gets difficult.