VLSI Architecture of Shared Multiplier Scheduling Scheme for Reconfigurable FFT/IFFT Processor

Abstract

This paper proposes VLSI Architecture of SMSS (Shared Multiplier Scheduling Scheme) for Reconfigurable FFT/IFFT processor. This architecture provides flexibility of selecting various FFT sizes (2, 4, 8, 16, 32, 64, 128 and 256) length, so that the hardware complexity of processor is reduced. The multipliers in SMSS based FFT processor are replaced with Vedic multiplier to improve speed of calculation. The proposed FFT/IFFT processors based on SMSS are designed using XILINX ISE Tool and modeled in Verilog HDL. The synthesis results shows that Area is reduced by 17% and speed is increased by 11%.In addition the proposed processor can be extended to any FFT sizes using additional stages.