Post Optimization of a Clock Tree for Vigor Give Noise Reduction

Abstract

The voltage drop incurred within the vigour supply in brand new VLSI chips to is a major hindrance referred to as vigor-provide noise. In sub one-volt give voltage, noise of very few enormous quantities millivolts factors circuit malfunction. The motive for energy provide noise is the quick and simultaneous transistor switching. At the same time the good judgment sign switching is unfold across the entire clock cycle, the switching of the clock tree and the sequential circuits are occurring at the same time, causing excessive local present peaks. The clock related transistor switching is the fundamental contributor to power give noise. This paper proposes to spread the switching of clock tree drivers in an try to decrease the peakcurrent, while preserving the clock sign pleasant and low skew at the some distance finish tree’s leaves where the sequential circuits are related. A strategy of mobilephone switching characterization was oncdeveloped for fast computation of peak-current and other indicators parameters. This computation is embedded in a branch and certain tree traversal. We endorse a novel optimization algorithm centered on clock tree delay-invariant branch transformation, replacing low-threshold by means of excessive-threshold and smaller measurement drivers. The algorithm used to be applied in forty nanometers design. We completed a reduction of 50% of clock-tree peakcurrent..