A Power-Efficient Floating-point Co-processor design

Abstract

In recent years computer applications have increased in their computational complexity. The processor designers to pay particular attention to implementation of the floating-point unit. And also due to drastically growing interests in low power and area efficient embedded processor, designers must establish the proper power and area strategies in their architecture while design new embedded processor core. This paper proposed efficient architecture to design a SPARC compatible floating-point co-processor, which is part of a SPARC compatible embedded processor, which implement the SPARC V8 floating-point instruction sat except for square root. In the proposed architecture, decoder stage of the integer unit pipeline generates the clock gating signals so that the unused floating-point co-processor execution pipeline can be clock-gated, which leads to lower the power dissipation and of floating-point co-processor.