Design and Analysis of Effective Data Encoding Techniques for Parallel Links in NOC

Abstract

A system-on-chip (SoC) combines the required electronic circuits of various computer components onto a single, integrated chip (IC).  SoC is a complete electronic substrate system that may contain analog, digital, mixed-signal or radio frequency functions. As the density of VLSI design increases, the complexity of each component in a system raises rapidly. Today’s SoC designers face a new challenge in the design of the on-chip interconnects beyond the evolution of an increasing number of processing elements. The main problems in SoC are wire delays, synchronization, uncertainity, power etc. hence to overcome these problems we go for Network on Chip (NoC). In the case of large-scale designs, network on chip is preferred as it reduces the complexity involved in designing the wires and also provides a well-controlled structure capable of better power, speed and reliability. For high-end system-on-chip designs, network-on-chip (NoC) is considered the best integrated solution. As the technology shrinks, the power dissipated by the links of a NoC starts to compete with the power dissipated by the other elements of the communication subsystem, namely, the routers and the network interfaces (NI). In this project, I analyzed a set of data encoding schemes aimed at reducing the power dissipated by the links of a NoC with small area overhead. The proposed schemes are general and transparent with respect to the underlying NOC fabric.