A Design Approach for Compressor Based Approximate Multipliers

Abstract

Approximate computing is best suited for error resilient applications, such as signal processing and multimedia. Approximate computing reduces accuracy, but it still provides meaningful and faster results with usually lower power consumption; this is particularly attractive for arithmetic circuits. In this paper, a new design approach is proposed to exploit the partitions of partial products using recursive multiplication for compressor-based approximate multipliers. Four multiplier designs are proposed using 4:2 approximate compressors. Extensive simulation results show that the proposed designs achieve significant accuracy improvement together with power and delay reductions compared to previous approximate designs. An image processing application is also presented to show the efficiency of the proposed designs.