A Novel approach of High Effective 64 Tap Fixed-Point DLMS Adaptive Filter

Abstract

Modern Field Programmable Gate Arrays (FPGAs) include the resources needed to design efficient filtering structures of   delayed least mean square adaptive filter. From the architecture, the low adaption delay, Area and power are synthesized. Fixed point implementation scheme architecture with bit level clipping is enhanced Adaptive filters learn the statistics of their operating environment and continually adjust their parameters accordingly. This system has been proposed for achieving lower adaptation-delay and to have area-delay-power efficient implementation. Optimization has taken place from the synthesis, the area, delay and power of the proposed system. An attempt is made to design efficient  architecture of adaptive filter.