Design and Implematation of 32-BIT MAC Unit Using Vedic Multiplier and Reversible Logic Gate

Abstract

A Vedic multiplier is composed by utilizing Urdhava Triyagbhayam sutra and the viper outline is finished by utilizing reversible rationale door. Reversible rationales are likewise the major prerequisite for the developing field of Quantum processing. The Vedic multiplier is utilized for the increase unit in order to lessen incomplete items and to get leading and smaller range .The reversible rationale is utilized to get less power. The MAC is outlined in Verilog HDL and the reproduction is done in Modelsim, Xilinx 14.2 and blend is finished in both RTL compiler utilizing rhythm and also Xilinx. The chip outline for the proposed MAC is additionally done.