Encoding Constant Coefficients to Contain the Least Non-Zero Digits

Abstract

Multimedia and Digital Signal Processing (DSP) programs (e.g., Fast Fourier Transform (FFT), audio/video CoDecs) execute a lot of multiplications with coefficients that don't change throughout the execution from the application. It's observed the pre-encoded NR4SD architectures tend to be more area efficient compared to conventional or pre-encoded MB designs regarding their performance within the cheapest possible clock period. Within this paper, we introduce architecture of pre-encoded multipliers for Digital Signal Processing programs according to off-line encoding of coefficients. A CSD-based prrr-rrrglable multiplier design was suggested for categories of pre-determined coefficients that share certain features. The suggested NR4SD encoding plan uses among the following teams of digit values. To be able to cover the dynamic selection of the 2’s complement form, all numbers from the suggested representation are encoded based on NR4SD except the most important one that's MB encoded. For this extend, the Non-Redundant radix-4 Signed-Digit (NR4SD) encoding technique, which utilizes the digit values, is suggested resulting in a multiplier design with less complex partial items implementation. The performance from the suggested designs is recognized as with regards to the width from the input figures. Extensive experimental analysis confirms the suggested pre-encoded NR4SD multipliers, such as the coefficients memory, tend to be more area and power efficient compared to conventional Modified Booth plan.