Design of a Parallel Self Timed Adder Circuit Using Recursive Approach



This brief proposes the design of a parallel self timed adder. It is based on an iterative formulation to perform multi bit addition. The operation will be parallel for the bits that does not need any chains or carry propagation. Hence, the design achieves more performance over random operand condition with no addition of any look ahead scheme and speed-up circuitry. A practical implementation is provided in this paper along with an extension of 4 block size when it is compared to the existing adder. Hence the implemented parallel self timed adder is of block size 8. The implementation is not at all complex and will not have any limits of high fan-outs. But a high fan-in gate is required as it is unavoidable for asynchronous logic and is achieved by the parallel connection of transistors. Simulations have been verified using Modelsim 6.5b tool that shows the practicality of design and Simulation of output waveforms are verified for the operation of addition.

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