Integrated Wireless Multi-Core Engineering Wireless Sensor Networks and Applications

S. Sashivardhan, T. Ravichandra babu


Technological advancements in the silicon industry, as predicted by Moore’s law, have enabled integration of billions of transistors on a single chip. To exploit this high transistor density for high performance, embedded systems are undergoing a transition from single core to multi-core. Although a majority of embedded wireless sensor networks (EWSNs) consist of single-core embedded sensor nodes, multi-core embedded sensor nodes are envisioned to burgeon in selected application domains that require complex in-network processing of the sensed data. In this project, an architecture for heterogeneous hierarchical multi-core embedded wireless sensor networks (MCEWSNs) as well as an architecture for multi-core embedded sensor nodes used in MCEWSNs is proposed.. This project also investigates the feasibility of two multi-core architectural paradigms symmetric multiprocessors (SMPs) and tiled many-core architectures (TMAs)V for MCEWSNs. This work compares and analyzes the performance of an SMP (an Intel-based SMP) and a TMA (Tilera’s TILEPro64) based on a parallelized information fusion application for various performance metrics (e.g., runtime, speedup, efficiency, cost, and performance per watt). Results reveal that TMAs exploit data locality effectively and are more suitable for MCEWSN applications that require integer manipulation of sensor data, such as information fusion, and have little or no communication between the parallelized tasks. To demonstrate the practical relevance of MCEWSNs, this project also discusses several state-of-the-art multi-core embedded sensor node prototypes developed in academia and industry.


Multi-Core, Engineering Wireless Sensor, Networks and Applications

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