A Novel Design Of Reliable Multiplier Using Adaptive Hold Logic

Suvarnaganti Rajasekhar, Gaddam Sekhar Reddy, Sannikanti Kishore Babu


Digital multipliers are  the most critical arithmetic functional units. The overall system performance depends upon the throughput of this multiplier. The positive bias temperature instability, occurs when an nmos transistor is under positive bias. The negative bias temperature instability effect occurs when a pmos transistor is under negative bias , increasing the threshold voltage of the pmos transistor, and reducing multiplier speed. Both effects degrade transistor speed, and in the long term, the system may fail due to timing violations. Therefore, it is important to design reliable high-performance multipliers. In this paper, we propose an aging-aware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect. Moreover, the proposed architecture can be applied to a column- or row-bypassing multiplier.

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