Analysis of Low Power 6T SRAM Using Tanner EDA Tool

Abstract

Memories are integral parts of most of the digital devices and hence reducing power consumption of memory is very important in improving the system performance, efficiency and stability. The requirement in present scenario is low power devices. Since these are critical component in high performance processors. Keeping this point in view, this paper proposes on 6T CMOS SRAM. The Proposed and conventional 16-bit SRAM has been designed and simulated for 180nm, 100nm and 90nm CMOS technologies. The 16-bit memory is organized in 4 x 4 forms (i.e. 4 rows and 4 columns). The whole circuit verification is done on the Tanner tool, Schematic of the SRAM cell is designed on  the S-Edit and net list simulation done by using T-spice and waveforms are analysed through the W-edit. An asymmetric configuration has been implemented to reduce this leakage power. 6T SRAM cell is the best asymmetric configuration used as caches.