Power Efficient Fixed Width Replica Redundancy Multiplier

Abstract

Most DSP applications runs on approximate values where as if u use normal elements which increases the area and the power, channel utilization also increases when we are dealing with the large bit length. Hence most architectural are turning towards fixed width multiplication. The present fixed with multipliers major problems are either lack of accuracy, replica blocks or improper compensation circuits. All drawbacks of earlier designs can be overcome by our proposed methods by designing fixed width multiplier without replica blocks and appropriate error compensation circuit. Replica blocks are removed from our design hence the overall area and the power of the system can be reduced drastically compare to that of the earlier designs.