Design of Dual Redundancy Can-Bus Controller with Very Efficient Memory Controller

Abstract

At present, the strategy of double excess CAN-bus is fundamentally executed by programming, with the goal that it has the impediments of low quality and terrible continuous execution. Based on the error taking care of control in CAN particular adaptation 2.0, an equipment excess administration unit is inventively advanced in this paper. In view of FPGA, a sort of redid Dual Redundancy CAN-bus Controller (DRCC) is planned. By downloading the IP Core into a XILINX's SPARTAN-3 chip to test, it has been confirmed that the plan could totally meet the prerequisite for high continuous execution and unwavering quality, with a brilliant prospect for what's to come