Design and Analysis of Aging-Aware and Area EfficientVedicMultiplier with Adaptive Hold Logic

Abstract

High speed, low power consumption is the key requirements to any VLSI design. The Area efficient multipliers play an important role. This paper presents an efficient implementation of a high speed, Vedic multiplier using aging aware technique and adaptive hold logic. This study presented the design and implementation of Vedic multipliers using XILINX. In this work, Modified Vedic multiplier is having least area. The Modified Vedic multiplier with adaptive hold logic and aging awareness make this efficient and also reliable. 32 bit signed multiplication and fractional multiplication is carried out and verified with around 10000 test patterns.