Design an Efficient Dual Logic Level Multiplier

Abstract

This paper represents the design of a Dual Logic Level Multiplier for 32*32 bit number multiplication. Modern computer system has a dedicated and very high speed unique multiplier. Therefore, this paper presents the design of a dual logic level multiplier. This proposed system hasseveral interconnected blocks. By extending bit of the operands it generates an additional product the dual logic level multiplier.Multiplication is performed by the dual logic level in efficient manner with less area and also it reduces delay i.e., speed is increased.