Design and Error Correction and Detection for Parallel Transformation

Abstract

This system makes protection against soft errors as a requirement for many applications in this portable world. Communications and signal processing systems have no exceptions to this trend. For some of the applications, brilliant option is to use algorithmic based fault tolerance (ABFT) techniques that are helpful to exploit the algorithmic properties for detecting and correcting the errors. Soft errors are responsible for a reliable threat to modern electronic circuits. Signal processing and communication applications are good enough to use ABFT. One of the best examples is fast Fourier transforms (FFTs) that are the basic building blocks in many systems. Many protection schemes have been proposed to detect and correct errors in FFTs. Among these, probably the uses of the Parseval or sum of squares check is the most widely known and used techniques. In these modern communication systems, it is most common to find several blocks operating in parallel. Recently, a technique that exploits this fact to implement fault tolerance on parallel filters has been proposed. This technique is first applied to save FFTs. Then, two schemes were implemented for the protection that combines the use of error correction codes and Parseval checks are evaluated. The results show that the proposed schemes can further reduce the implementation cost of protection. The proposed architecture of this paper analysis the logic size, area and reduction of power consumption using Xilinx.