Advanced Effective Risc Processor Design Using Built-In Self-Test Repair

Abstract

Built-in self-test repair (BISTR) technique has been most widely used to test repair embedded RISC processor. This paper proposes a reconfigurable BISTR (ReBISTR) scheme to test repairing RISC processor with different sizes and redundancy organizations. An efficient redundancy BIST algorithm is proposed to allocate redundancies of defective RISC processor. In the ReBISTR, a reconfigurable built-in self-test and test repair redundancy analysis is (ReBIRA) design circuit is to perform the redundancy algorithm for various RISC. Also, an adaptive reconfigurable methodology is proposed to reduce the test repair setup time when the RISC are operated in normal mode. Due to the complexity of memory architectures, the possibility of occurring manufacturing defects is high. Hence memory testing is necessary. Built inSelf-Testrepair (BISTR) has been proven to be most cost-effective and widely used solutions for memory testing. BISTR technique is used to reduce test repair time. The design architecture is simulatedin Xilinx ISE 14.7 tools.