Design Aging Awaredual Logic Level Multiplier

Abstract

This paper presents the design aDual logic level [D.L.L] multiplierfor 32*32bit number multiplication. Modern computer system is a dedicated and very high speed unique multiplier. Therefore, this paper presents the design aDuallogic level multiplier. The proposed systemconsists of two stages preprocessing and post processing interconnected blocks. By extending bit of the operands and generating an additional product the Duallogic level multiplier is obtained. Multiplication operation is performed by the Duallogic levelis efficient with the less area anditreduces delay i.e., speed is increased.