Built-in self-test technique for Radom access Memories (RAMs)

Abstract

Very large Scale Integration (VLSI) has created a dramatic impact on the growth of microcircuit technology. It has not only reduced the dimensions and also the value, but conjointly accumulated the complexes of the circuits. The improvements have resulted in important performance/ cost benefits in VLSI systems. Transparent BIST schemes for RAM modules assure the preservation of memory contents throughout –periodic testing. As the speed power area are the constraints of memory testing. Built in Self-Test repair (BISTR) has been proven to be most cost-effective and widely used solutions for memory testing. BISTR technique is used to reduce test repair time. The design architecture is simulated in Xilinx ISE 13.2 tools. 

Keywords: SOC, BIST, BISTR, Test Pattern Generator, FPGA