An Efficient High Secured Architecture for M-Turbo Decoders Using S- Box

Abstract

To accelerate the majority logic decoding of difference set low density parity check codes the error detection   in memory applications was proposed. This is useful as majority logic decoding can be implemented serially with simple hardware but requires a large decoding time. For memory applications, the increase of the memory access time takes place. S-Box Codes are the class of linear block codes which provide near capacity performance on large collection of data transmission channels.