Design an Aging Aware Hybrid Logic Level Multiplier

Abstract

 This paper presents the design of a Hybrid logic level [H.L.L] multiplier for 32*32bit number multiplication. Modern computer system is a dedicated and very high speed unique multiplier. Therefore, this paper presents the design a Hybrid logic level multiplier. The proposed system generates M, N and interconnected blocks. By extending bit of the operands and generating an additional product the Hybrid logic level multiplier is obtained. Multiplication operation is performed by the Hybrid logic level is efficient with the less area and it reduces delay i.e., speed is increased.