Design of High Speed Truncated Parallel Prefix Adder

Abstract

: In this paper discussed about a carry skip adder (CSKA) structure with P.P.A compared with the conventional adder. A parallel-prefix adder gives the best performance in VLSI design. However, performance of P.P.A adder through black cell takes huge memory. So, gray cell can be replaced instead of black cell which gives the Efficiency in P.P. Adder. The proposed system consists of three stages of operations they are pre-processing stage, carry generation stage, post-processing stage. The pre-processing stage focuses on propagate and generate, carry generation stage focuses on carry skip generation and post-processing stage focuses on final result