Design of Pulsed Latch Based Shift Register with Reduced Power and Area

Abstract

Power consumption and Area reduction is a major role in sequential circuit design .A novel approach to design a pulsed latch based shift register with reduced area and power is proposed.. In this the, conventional data Flip flops are replaced with pulsed latches to reduce area occupation .This method solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal. In the existing system, shift register uses single pulsed clock signal for data transition, which consumes more power. The shift register uses a small number of the pulsed clock signals by grouping the latches to several sub shifter registers and using additional temporary storage latches. To minimize power consumption multiple non overlap delayed pulsed clock signal scheme is proposed for data synchronization in a multi bit shift register. The proposed system will be carried out using Tanner T- Spice.