An Efficient Flexible Dsp Architecture For Error Tolerant Applications Employing Carry Save Arithmetic

Abstract

In this paper, we present a low power 32-bit multiplier design, by using Carry Save Adder (CSA). The multiplier design shown in this paper is modeled using Verilog language for 32-bit unsigned data. Optimizing speed and power constraints have become challenging tasks in the design of any reliable and efficient integrated circuit. This paper sets up the design of a 32- bit multiplier which is of high speed, and has low power consumption. By reducing the generated partial products the speed of the multiplier can be increased. There are many ways by which we can reduce the number of partial products generated in a multiplication process. Wallace tree multiplier method is one of them.Therefore, minimizing the number of half adders used in a multiplier will reduce the circuit complexity.