HIGH SPEED AND AREA EFFICIENT TRUNCATING MULTIPLIER FOR D.S.P APPLICATIONS

Abstract

In digital signal processing multiplication is frequently required. Parallel multipliers provide a high-speed method for multiplication, but require large area for VLSI implementations. A rounded product is desired to avoid growth in word size, in most signal processing applications. Thus an important design goal is to reduce the area requirement of the rounded output multiplier. This paper presents Field Programmable Gate Array (FPGA) which uses Very High Speed Integrated Circuit Hardware Description Language (VHDL) for the implementation of standard and truncated multiplier.  Truncated multiplier is a good candidate for digital signal processing (DSP) applications such as finite impulse response (FIR) and discrete cosine transform (DCT) etc.  Instead of standard parallel multipliers the significant reduction in FPGA resources, delay, and power is achieved by using truncated multipliers when the full precision of the standard multiplier is not required. The total project execution is done at Xilinx14.7 Spartan-3AN FPGA device.