Design of Low-Power Full Adder Using GDI Structure and Hybrid CMOS Logic Style

Abstract

— In this paper, a hybrid 1-bit full adder design using GDI structure is employed. The circuit was implemented using TANNER EDA tools in 180 and 90-nm technology. Performance parameters such as power, delay were compared with the existing designs such as conventional cmos adder, hybrid cmos adder, mirror adder, transmission gate adder, and so on. In comparison with the existing full adder designs, the present implementation was found to offer significant improvement in terms of power and speed.