A High Speed Vlsi Architecture For Image Deinterleaver For Compression

peddi Surekha, ambati Sridevi


Thecommunity of the research in the last few years has received significant attention from the field of approximate computing, particularly in different signal processingcontext. The compression algorithms of the image deinterleaver and video such asMPEG and JPEG and so on, which can be exploited to realize the implementations ofhighly power-efficient of these algorithms.  However, existing approximate architectures naturally fix the approximations of hardware levels statically and are not adaptive to the input data. This project addresses this issue through proposing a reconfigurable approximate for encoders of MPEG which optimizes consumption of power with the aim of maintaining a particular peak signal-to-noise ratio threshold for any video. I design reconfigurable adder/ subtract blocks, and later integrate these blocks in the special levels all the video in to image deinterleavers these image deinterleavers will be converted to digital form and then compression of theimage deinterleaver.

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