A Novel Design of Multiple Error Correction Codes with Fast Decoding For a Subset of Critical Bits

A. Raghava Raju, Madala Naga Swapna


To protect data stored in memories and registers multiple error correction are widely  used. A few control bits are added to the data in some applications such as networking, to facilitate their pressing. For example, flags to mark the start or the end of a packet are widely used. Therefore to protect both data and the associated control bits, it is important to have SEC Codes. The most attractive feature of these codes it to provide fast decoding of the control bits, as these are used to determine the processing of the data and are commonly on the critical timing path. A few additional control bits is presented to extend SEC codes. The derived codes support fast decoding of the additional control bits and are therefore suitable for networking applications.

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