A Novel Security Cryptography Using Reversible Gates



In this paper, a novel architecture of encryption and decryption using high security technique for the VLSI implementation for encryption and decryption using reversible data. The pre-defined keys are required for each input for both encryption and decryption that are generated in real-time by the key-scheduler module by expanding the initial secret key and thus used for reducing the amount of storage for buffering. S-boxes are used for the implementation of the S.R, M.C and inverses S.R & M.C shared between encryption and decryption. The round keys needed for each round of the implementation are generated in real-time. The forward and reverse key scheduling is implemented on the same device, thus allowing efficient area minimization. Rather Than Using logical gates we are using PG gate for speed of operation. The pipelining is used after each standard round makes fast of operation to enhance the throughput and shift row mix column technique gives high security. The fault tolerance gives error free output than existed cryptography applications. These total design is designed with reversible gates to make less power for high speed applications. 

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